I. Who Built Flyer? The Prime Contractor and Supply Chain

AFRL has not publicly named the integrator of TI-23 at the June 2026 ribbon-cutting — a routine omission for DoD procurement, where vendor identity and system architecture below the top-level headline figures are often withheld on acquisition sensitivity grounds. However, the public record is sufficiently specific to identify the most probable prime with high confidence.

In September 2021, the DoD High Performance Computing Modernization Program awarded Penguin Computing — now operating as Penguin Solutions, a subsidiary of Smart Global Holdings (SGH) — two contracts collectively valued at $68 million. Those contracts called for delivery of Penguin TrueHPC supercomputing platforms, plus managed services and high-performance storage, to exactly two sites: the Air Force Research Laboratory DSRC and the Navy DSRC. The award predates the formal TI-23 program designation, but the number and location of the contracted systems precisely matches the TI-23 Flyer (AFRL, unclassified) and TI-23 Raven (AFRL, classified) pair. Penguin's own president, Sid Mair, confirmed at contract award that the platforms would be used for "the highly complex problems the user community is tasked with solving" and cited AMD and NVIDIA partnerships as the enabling semiconductor relationship.

TI-23 Probable Supply Chain — Based on Public Procurement Record

  • System Integrator (Prime)
    • Penguin Solutions
    • Subsidiary of Smart Global Holdings (SGH); formerly Penguin Computing. Winner of $68M DoD HPCMP contract (Sep 2021) for two TrueHPC platforms at AFRL and Navy DSRCs. Penguin has offered HPC solutions since 1998; acquired by SGH (Cayman Islands-based) for $85M in 2019.
  • GPU Accelerator (Confirmed)
    • NVIDIA Corporation
    • NVIDIA GPU model unspecified at ribbon-cutting. Brig. Gen. Wickert cited "NVIDIA chips and GPUs" explicitly. Penguin's TrueHPC platforms for DoD have used NVIDIA H100 or A100-class datacenter GPUs in recent configurations. Export-controlled; not available to Chinese or sanctioned entities.
  • CPU (Precedent Architecture)
    • AMD
    • Raider (TI-21, the immediately preceding AFRL system) used AMD CPUs + NVIDIA GPUs per 2022 AFRL DSRC disclosure. The TI-23 architecture is unconfirmed at the CPU level; AMD EPYC is standard in Penguin TrueHPC configurations. TI-23 may also follow the full AMD + NVIDIA GPU-accelerated pattern used in El Capitan and Frontier.
  • High-Performance Storage
    • Likely DDN or equivalent
    • 18 PB storage capacity confirmed. Previous AFRL DSRC generations (HPE SGI 8600 era) used DDN Lustre parallel storage; Penguin TrueHPC configurations typically offer DDN or IBM Spectrum Scale. Specific vendor not publicly disclosed for TI-23.
  • Interconnect Fabric
    • InfiniBand (likely) or HPE Slingshot
    • Not publicly disclosed. Raider used Penguin's integrated fabric. At 186,000 processors, a high-bandwidth low-latency interconnect (NDR InfiniBand at 400 Gbit/s per port, or HPE Slingshot) is required to prevent I/O bottlenecks in coupled-field hypersonic simulations.
  • Network Backbone (DREN)
    • Verizon
    • DREN 4, the DoD Research and Engineering Network connecting all five DSRCs, is operated under a commercial services contract awarded to Verizon in 2021. Supports 1–100 Gbit/s data transfer; IPv6-native with IPv4 compatibility. More than 210 DoD sites connected.
  • Managed Services
    • Penguin Solutions
    • Included in 2021 contract. Bryon Foster (AFRL DSRC director) confirmed 24/7/365 operational commitment; Penguin's managed services team provides system administration, user support, and continuous operation assurance for DoD HPCMP centers.

One earlier generation of AFRL DSRC systems — a set of four SGI 8600 clusters commissioned before the Raider era — was supplied by Hewlett Packard Enterprise (HPE) and powered by 24-core Intel Xeon Scalable processors with Intel Omni-Path fabric and DDN Lustre storage at 12 petabytes per system. That HPE/Intel architecture has given way to the AMD CPU + NVIDIA GPU architecture across recent DoD HPCMP insertions, consistent with the broader industry migration toward heterogeneous compute for mixed HPC/AI workloads. Flyer's NVIDIA GPU content is the clearest signal of this architectural shift: the same class of datacenter GPU that trains large language models at scale is now the core computational substrate for aerothermal shock physics at the Air Force Research Laboratory.

II. Where Flyer Stands in the Global Supercomputer Order

Benchmarked at 8.7 petaflops, Flyer does not approach the upper tier of the current global TOP500. As of the June 2025 TOP500 list, the entry threshold (rank 500) stood at 2.57 petaflops — meaning Flyer would rank somewhere in the vicinity of the 200th to 250th position worldwide, a mid-table placement. The three leading U.S. Department of Energy machines occupy a different computational order of magnitude entirely: El Capitan at Lawrence Livermore National Laboratory tops the list at 1,742 petaflops (1.742 exaflops), Frontier at Oak Ridge at 1,353 petaflops, and Aurora at Argonne at 1,012 petaflops. Europe's JUPITER system at Forschungszentrum Jülich in Germany, inaugurated in September 2025, became the continent's first exascale-class system at 1,000 petaflops.

Global Supercomputer Landscape — Selected Systems, June 2026
System Country / Operator Peak (Rmax) Architecture TOP500 Rank Primary Mission
El Capitan USA / LLNL 1,742 PFlop/s HPE Cray EX, AMD EPYC + MI300A #1 Nuclear stockpile stewardship
Frontier USA / ORNL 1,353 PFlop/s HPE Cray EX235a, AMD EPYC + MI250X #2 DOE open science
Aurora USA / Argonne NL 1,012 PFlop/s HPE Cray EX, Intel Max Series #3 AI + science
JUPITER Booster Germany / FZ Jülich ~1,000 PFlop/s NVIDIA GH200 (Grace Hopper) #4 European research
Tianhe-3 "Xingyi" China / NUDT Tianjin ~1,300–1,700 PFlop/s (est.) Phytium CPUs + Matrix-3000 (domestic) Not submitted Defense/AI — classified
Sunway OceanLight China / NSC Wuxi ~1,000+ PFlop/s (est.) Sunway Microelectronics (domestic) Not submitted Ocean modeling / defense
Sunway TaihuLight China / NSC Wuxi 93 PFlop/s Domestic SW26010 manycore #24 (Nov 2025) General research
Flyer (TI-23) USA / AFRL WPAFB 8.7 PFlop/s Penguin TrueHPC, NVIDIA GPUs, AMD CPUs (prob.) ~200–250 (est.) Defense RDT&E (unclassified)
Raven (TI-23) USA / AFRL WPAFB ~5–6 PFlop/s (est.) Penguin TrueHPC (classified config.) Not submitted Defense RDT&E (classified)
Raider (TI-21) USA / AFRL WPAFB 12 PFlop/s Penguin, AMD + NVIDIA ~50 (at commission, 2023) Defense RDT&E (predecessor)

* Flyer's TOP500 rank is an estimate; AFRL DSRC systems are not routinely submitted to the TOP500 list. Raven specifications are estimated from the combined 14 PFlop/s target minus Flyer's 8.7 PFlop/s. Chinese exascale figures reflect unverified intelligence community and open-source assessments; neither system has been formally benchmarked on HPL. Sources: TOP500.org, Data Center Dynamics, Tom's Hardware, Wikipedia, NextPlatform.

The China comparison requires careful handling. On the public TOP500 list, China's highest-ranked submission as of November 2025 is the 2016-vintage Sunway TaihuLight at 93 petaflops — ranking 24th, more than ten times slower than Flyer's own predecessor, Raider. This number is almost universally acknowledged in the HPC community as a profound underrepresentation of China's actual computational capability. Since 2017, Chinese institutions have progressively withdrawn new systems from TOP500 submissions, offering Gordon Bell Prize competition papers as the primary evidence of continued development instead.

By most credible open-source estimates, China operates at least two exascale-class systems. Tianhe-3 (nicknamed "Xingyi"), developed by the National University of Defense Technology and housed at the National Supercomputing Center in Tianjin, has been estimated at approximately 1.3 exaflops sustained (1.7 exaflops peak) on HPL-equivalent benchmarks — performance that would place it between Frontier and El Capitan if submitted to TOP500. The Sunway OceanLight at the National Supercomputing Center in Wuxi is estimated at comparable throughput. A third exascale-class system, allegedly built by China's Sugon (now operating under U.S. entity-list restrictions that blocked its access to AMD Hygon CPUs) and housed at the Shenzhen supercomputing center, has an uncertain status. China's Ministry of Industry and Information Technology stated in mid-2024 that China's aggregate installed computing capacity across all systems had reached approximately 230 exaflops of theoretical peak — a figure that, taken at face value, represents aggregate capacity of the entire government, commercial, and research sectors, not individual machine peak performance.

"China's OceanLight system … at least seems to aspire to exaflop-sized performance — albeit one that remains inscrutable to international standards." NextPlatform, February 2024, citing HPC community analysis

The geopolitical dimension of this opacity is significant: U.S. export controls imposed since 2019 have systematically denied China access to advanced NVIDIA H100 and A100 GPUs — the same accelerators almost certainly powering Flyer — and have restricted Huawei and Sugon from U.S.-origin technology. China's response has been to develop indigenous alternatives, including Huawei's Ascend series and domestic interconnect fabrics, at considerable cost in both money and performance parity. The Tianhe-3 and OceanLight systems are built on entirely domestic silicon from Phytium (CPUs) and Sunway Microelectronics respectively — a deliberate supply-chain independence that trades performance efficiency for invulnerability to U.S. sanctions. From AFRL's operational standpoint, the direct performance comparison is less strategically relevant than the access-and-security envelope: Flyer operates within a classified-adjacent, export-controlled, security-vetted infrastructure that no Chinese entity can access, while Chinese defense supercomputing operates in a comparable walled garden that U.S. researchers cannot reach.

III. What 8.7 Petaflops Actually Buys for Hypersonic CFD

The engineering claim that matters most for AFRL's mission is not where Flyer ranks on TOP500 but what it enables in hypersonic research that predecessor systems could not accomplish on acceptable timescales. The physics problem is instructive.

A hypersonic vehicle traveling at Mach 5 or above generates a shock-layer environment in which the flow chemistry, heat transfer, and boundary-layer dynamics are tightly coupled across multiple physical phenomena: high-temperature gas dissociation and ionization, turbulent boundary-layer transition (which determines transition from laminar to turbulent heat flux — a factor of three to seven in heating rate), ablation and oxidation of thermal protection materials, and plasma sheath formation that attenuates radio-frequency communications. Each of these phenomena operates on different length and time scales, and their accurate coupled representation requires fine spatial resolution that scales computational cost as roughly the cube of the linear resolution factor. Halving the grid spacing in all three dimensions multiplies computational cost by approximately eight. Running to higher Mach numbers, longer bodies, or more complex geometries compounds this further.

AFRL's own documentation for its predecessor Raider system (TI-21) illustrated the practical consequence: a Navy simulation project that previously required six months of continuous compute time on the available DSRC hardware was cut to three weeks on Raider's 12-petaflop architecture — a factor of roughly eight in elapsed time. The Flyer-Raven TI-23 combination offers approximately 1.17 times Raider's total performance in direct petaflop terms (14 combined versus 12), but GPU-accelerated HPC does not scale linearly with headline petaflop count for all workload types. The key enabler is the NVIDIA GPU's performance on the specific linear algebra kernels that dominate CFD solvers: sparse matrix-vector products, fast Fourier transforms for spectral methods, and the iterative linear solvers (GMRES, multigrid) that consume most clock cycles in Reynolds-Averaged Navier-Stokes (RANS) and Large Eddy Simulation (LES) codes.

AFRL's computational aeroscience community uses several DoD HPCMP-maintained and community-developed codes for hypersonic work: Kestrel (the HPCMP CREATE Air Vehicles code), OVERFLOW (NASA/AFRL), and US3D (University of Minnesota, developed under AFRL-funded research). These codes have been progressively GPU-ported over the past five years, and all three benefit directly from Flyer's NVIDIA GPU density. Purdue University's AFRL-sponsored hypersonic turbulence research — which uses HPCMP computing allocations to design passive surface treatments for boundary-layer transition delay — provides a concrete example: computational simulation campaigns design the surface geometry, physical tunnel tests at AFRL's Mach 6 Ludwieg tube validate the results, and the agreement between prediction and experiment determines whether the next simulation campaign is warranted. The HPCMP Frontier ceramics program extended this paradigm to materials discovery, predicting approximately 900 candidate thermal protection compounds — a screening campaign that would have been physically infeasible through bench synthesis.

At 8.7 petaflops with GPU acceleration, Flyer enables LES campaigns on full-vehicle hypersonic geometries that were previously limited to reduced-geometry or 2D-symmetric configurations on RANS solvers at lower fidelity. The practical implication: aerothermal predictions at the nose cap, control surface junction, and inlet throat of a hypersonic glide vehicle can now be run in high-fidelity LES in days rather than months, enabling design-space exploration that was previously incompatible with acquisition program timelines.

IV. Operations: How Projects Are Scheduled and Prioritized

An Engineers Guide to Scheduling a CFD job on Flyer. Flyer does not operate as a dedicated single-purpose machine for any one research program. Like all HPCMP DSRC systems, it is a shared national resource serving hundreds of concurrent projects across the services, agencies, and sponsored civilian and contractor researchers. The allocation and scheduling architecture that governs who gets core-hours, when, and at what priority is a two-layer system: a resource allocation governance layer that determines how many core-hours each project receives per fiscal year, and a job scheduling layer that determines when allocated compute jobs actually run.

At the governance layer, the HPCMP's Resource Management team collects and manages computational requirements through the Portal to the Information Environment (pIE), coordinated with Service/Agency Approval Authorities (S/AAA) — the branch-level gatekeepers who validate that a proposed project aligns with DoD mission priorities and that the requesting organization has appropriate clearances and DoD sponsorship. All users must have a DoD government scientist or engineer as a sponsor; principal investigators may be from government, industry, or academia. The S/AAA approval is required before any core-hour allocation is granted.

Projects are allocated resources in five general tiers, each with distinct proposal requirements, priority treatment in the scheduler, and compute quantum available:

● URGENT
Urgent Projects
DoD HPCMP-designated. Bypass normal queue ordering; immediate resource claim. Reserved for time-critical operational or acquisition crises where delay constitutes unacceptable mission risk. Requires HPCMP Director-level approval.
● HIGH PRIORITY
High Priority Projects
Pre-authorized elevated queue access. Jobs in the "high" Slurm queue jump ahead of standard allocations. Typically reserved for acquisition program milestones, test and evaluation support, or Congressional-directed priorities.
● FRONTIER
Frontier Projects
Multi-year commitments of exceptional compute allocations — resources that would not be achievable through standard channels. Competitive proposal process, reviewed by the High Performance Computing Advisory Panel (HPCAP). Eligible PIs include government, industry, and academia with DoD sponsor. Dedicated Slurm queue partition.
● AE PROGRAM
Acquisition Engineering
Dedicated track for acquisition engineering, mission engineering, and T&E workflows tied to DoD programs of record. Access to compute resources, DREN network access, and specialized modeling/simulation software tools (CREATE suite). Managed separately from S&T allocations.
● STANDARD
Standard Allocations
The baseline tier. Annual core-hour allocations via S/AAA approval. Jobs submitted to standard, large, background, or debug Slurm partitions with fair-share scheduling. Background queue allows low-priority opportunistic jobs (up to 10 concurrent per user); debug queue is limited to short verification runs.

At the job scheduling layer, Flyer (and Raider before it) uses the Slurm Workload Manager — the same scheduler that powers more than 60 percent of TOP500 systems globally, including the Tianhe-2 in China. Slurm manages the assignment of specific compute nodes to queued jobs based on resource availability, time limits, and priority scores. Priority is computed from a combination of factors: project allocation tier (Urgent/High/Frontier jobs receive favorable treatment), fair-share weighting (teams that have recently consumed large fractions of their allocation receive lower instantaneous priority to equalize system access over time), job size and wall-clock time limits, and queue-specific policies set by AFRL DSRC system administrators.

The HPCMP additionally offers Dedicated Support Partitions (DSPs) — reserved node sets held for specific programs that require guaranteed turnaround, analogous to a dedicated laboratory instrument that cannot be preempted by other users. DSPs are a premium resource available only to programs that have justified the need for guaranteed access windows, such as large-scale time-sensitive test support campaigns where computational results must be available before a physical test event proceeds.

For Frontier-class projects — the largest and most computationally demanding campaigns — the proposal process is formally competitive. Proposals are reviewed by the High Performance Computing Advisory Panel (HPCAP), a board of senior DoD computational science and engineering experts, and must demonstrate both scientific or engineering rigor and a clear connection to DoD acquisition or S&T mission outcomes. Multi-year commitments are evaluated at annual Intermediate Program Reviews (IPRs), and continued funding is contingent on demonstrated progress. The HPCMP Institute program, a parallel track, funds software development efforts that produce deployable tools for the wider HPCMP user community — CREATE-class codes and similar deliverables — and imposes the same IPR discipline with weekly activity reports and monthly financial reporting.

"Sometimes even before the system is running, we're ordering the next one. These systems are so large, and it takes so much to build them, get them in the building and up and running that there is a continual process." Bryon Foster, Director, AFRL DoD Supercomputing Resource Center (2023, discussing the TI-23 procurement)

The operational rhythm that results is one of perpetual queuing under a priority framework that mirrors the broader DoD funding hierarchy: programs of record with acquisition milestones get AE or High queue access; large multi-year S&T campaigns compete for Frontier status; smaller research efforts and academic partners operate in the standard tier under fair-share rules that prevent any single group from monopolizing the system. The 24/7/365 operational commitment means Flyer's 186,000 processors are never intentionally idle — unused cycles are consumed by lower-priority background queue jobs rather than allowed to go to waste. Over a projected five-year service life, this continuous-utilization model underpins the $800 million lifetime savings figure: every hour of simulation delivered is an hour of physical testing avoided.

V. The Supply Chain Vulnerability Underneath Flyer's Capability

A final dimension of Flyer's significance that received no attention at the ribbon-cutting but is implicit in its architecture: the entire system depends on NVIDIA GPU silicon that is manufactured, at leading edge, at TSMC in Taiwan — and is now subject to the same export control architecture that restricts Chinese access to that same silicon. The U.S. maintains its lead in deployable GPU-accelerated supercomputing precisely because NVIDIA H100 and successor chips cannot be legally exported to China, and because China's domestic accelerator industry (Huawei Ascend, Biren, Cambricon) has not yet closed the performance gap at scale. AFRL's Flyer is therefore simultaneously a national defense capability and a proof point in an ongoing industrial policy contest: the U.S. bet that maintaining NVIDIA export restrictions and investing in domestic GPU-dense HPC infrastructure compounds American advantage in simulation-based weapons development faster than China can build comparable capability from domestically produced silicon.

Whether that bet holds depends on China's pace of domestic semiconductor development — a question that has as much bearing on AFRL's next supercomputer procurement as any doctrinal priority or budget line. From Wright-Patterson's secure facility on Area B, Flyer's NVIDIA GPU nodes run a race that began not in Dayton but in the foundry halls of Hsinchu and the national supercomputing centers of Tianjin and Wuxi.