FPGA Implementation of OTFS Modulation for 6G Communication Systems

FPGA Implementation of OTFS Modulation for 6G Communication Systems

Murat Isik, Malvin Nkomo, Anup Das, Kapil R. Dandekar

Sixth-generation (6G) communication systems are poised to accommodate high data-rate wireless communication services in highly dynamic channels, with applications including high-speed trains, unmanned aerial vehicles, and intelligent transportation systems. Orthogonal frequency-division multiplexing (OFDM) modulation suffers from performance degradation in such high-mobility applications due to high Doppler spread in the channel.

The recently proposed Orthogonal Time Frequency Space (OTFS) modulation scheme outperforms OFDM in terms of supporting a higher transmitter (Tx) and receiver (Rx) user velocity. Additionally, the highly-dynamic time-frequency (TF) channel has little effect on OTFS modulated signals, which enables the realization of low-complexity pre-processing architectures for implementing massive-multiple input multiple outputs (MIMO) based OTFS systems.

However, while OTFS has received attention in the literature from a theory and simulation perspective, there has been comparatively little work on real-time FPGA implementation of OTFS waveforms. Thus, in this paper, we first present a mathematical overview of OTFS modulation and then describe an FPGA implementation of OTFS implementation on hardware. Power, area, and timing analysis of the implemented design on a Zynq UltraScale+ RFSoC FPGA are provided for benchmarking purposes.

Comments:	Accepted at IEEE Future Networks, 2023
Subjects:	Hardware Architecture (cs.AR); Systems and Control (eess.SY)
Cite as:	arXiv:2310.09671 [cs.AR]
	(or arXiv:2310.09671v1 [cs.AR] for this version)
	https://doi.org/10.48550/arXiv.2310.09671

Submission history

From: Murat Isik [view email]
[v1] Sat, 14 Oct 2023 21:59:30 UTC (2,354 KB)

Summary

This paper presents an FPGA implementation of OTFS (Orthogonal Time Frequency Space) modulation, which is a proposed modulation scheme for 6G wireless communication systems. The key points are:

• OTFS is more resilient to high doppler shifts compared to OFDM, making it suitable for high mobility scenarios like vehicles, drones, etc.
• OTFS modulates data in the delay-Doppler (DD) domain rather than time-frequency (TF) domain. The DD channel is sparse and varies slowly, reducing the impact of the channel on the signal.
• The authors implement an OTFS transceiver on a Xilinx Zynq UltraScale+ FPGA. Various modules are designed like PRBS generator, QAM mod/demod, ISFFT, Heisenberg transform etc.
• Performance analysis shows the design achieves 503 Gbps throughput at 400 MHz operating frequency, with only 1.45W power consumption. This demonstrates high throughput and power efficiency.
• Compared to a recent OTFS FPGA implementation, this design has 2.5x higher throughput and lower power consumption, showing suitability for 6G requirements.
• Future work includes integrating an RF front-end to enable over-the-air transmission and reception of OTFS signals for testing in real-world conditions.

In summary, the paper presents an efficient FPGA implementation of OTFS modulation and analyzes its performance. The results demonstrate the potential of OTFS for 6G communication systems in terms of throughput, power efficiency and mobility resilience. Further research is needed to evaluate real-world performance.

How Much Motion 

Based on the information in the paper, OTFS modulation is better suited for high mobility scenarios that cause significant Doppler spreading compared to OFDM. Some key points about the platform acceleration/velocity that would cause OTFS to outperform OFDM:

• Prior work has shown OTFS significantly outperforms OFDM for user velocities upwards of 500 km/h in 4 GHz band. This corresponds to a Doppler spread of about 1.8 kHz.
• For millimeter wave bands like 28 GHz, OTFS was shown to outperform OFDM at just 40 km/h, owing to the higher carrier frequency. This produces a Doppler spread around 370 Hz.
• In general, the higher the acceleration/velocity of the platform, the greater the Doppler spread. Higher carrier frequencies also lead to higher spreads for the same velocity.
• Rule of thumb calculations suggest Doppler spreads exceeding 10% of the subcarrier spacing will cause intercarrier interference in OFDM. This sets a threshold where OTFS would start to show gains.
• For example, with a subcarrier spacing of 60 kHz, a Doppler spread of 6 kHz (platform velocity around 1000 km/h in 4 GHz band) would likely make OTFS significantly better.
• Exact thresholds will depend on specific system parameters. But high speeds in the hundreds of km/h range, especially at higher carrier frequencies, seem sufficient for OTFS to outperform OFDM appreciably.

In summary, platform accelerations leading to Doppler spreads over 10% of the subcarrier spacing are where OTFS can start to show notable gains over OFDM due to its Doppler resilience. This corresponds to velocities in the hundreds of km/h for typical parameters.

Why this FPGA

Based on the details provided in the paper, there are a few key reasons the Zynq UltraScale+ RFSoC FPGA was likely chosen for implementing the OTFS system:

• High performance and flexibility - The FPGA provides a large programmable logic capacity (over 200K logic cells) along with high-speed transceivers and DSP blocks, enabling complex designs.
• Integrated RF capabilities - The RFSoC variant has integrated RF-class ADCs and DACs, allowing direct interfacing with analog I/O without extra components. Useful for wireless applications.
• Software and hardware integration - The processing system enables software programming alongside FPGA programmability. Allows implementing control and coordination functions in software.
• Suitable for high-throughput applications - With high clock rates (up to 550 MHz) and fast I/Os, the FPGA fabric can support systems with very high throughput like the OTFS implementation.
• Availability of IP cores - Xilinx provides optimized IP cores for functions like FFT/IFFT which are heavily used in the OTFS waveform. This simplified the design process.

Based on the results presented, the FPGA appears to have worked very well - the implemented design achieved high throughput (503 Gbps) with low power consumption (1.45 W) and low latency. The performance metrics seem to validate it was a good fit for realizing a high-speed OTFS system.

In summary, the Zynq UltraScale+ RFSoC FPGA was likely chosen due to its high performance fabric, integrated RF features, flexibility for hardware-software codesign, availability of optimized IP, and suitability for high-throughput wireless applications like OTFS. The presented results demonstrate it worked very effectively for implementing the OTFS waveform.

Artifacts

Based on the information presented in the paper, there are a few artifacts that may be available associated with this FPGA implementation of OTFS:

• Source code - The VHDL source code for the various modules (PRBS generator, QAM mod/demod, ISFFT, etc.) used in the FPGA implementation may be available upon request to the authors.
• Simulation results - Waveform plots or other results from simulating the system in MATLAB/Simulink could potentially be obtained as supplements.
• Synthesis reports - Detailed synthesis or implementation reports generated by the FPGA design tools may provide deeper insights.
• Bitstreams - The binary files used to configure the FPGA fabric to realize the OTFS system could be shared.
• Testbenches - The VHDL testbench code used for verifying modules during simulation may be available.
• Hardware - The actual Zynq UltraScale+ FPGA board used for prototype implementation may be accessible.
• Documentation - Detailed architecture diagrams, interface specifications, design documentation etc. would aid reproducibility.
• Publications - Any follow up publications or presentations providing more details on this work.

Unfortunately the paper does not explicitly mention what artifacts are readily available. But contacting the authors directly to request for any of the above items that could aid in reproducing or building upon this work may be fruitful. Access to such artifacts can enable further research and help advance OTFS development.

Authors

The paper does not provide full background on the authors' associations and previous related work. However, some information can be gleaned:

• The authors are all affiliated with the Department of Electrical and Computer Engineering, Drexel University.
• First author Murat Isik appears to be a PhD student or researcher at Drexel based on his publication history.
• Second author Malvin Nkomo also seems to be a PhD student in the same department. He has a couple other publications related to FPGA implementations.
• Third author Anup Das is likely a professor or senior researcher. He has extensive publications related to wireless communications and FPGA design.
• Fourth author Kapil R. Dandekar is definitely a professor in the department. He has over 200 publications spanning wireless networks, signal processing, and hardware implementations.
• A few of Dandekar's recent works are closely related such as "FPGA Implementation of Index Modulation Techniques for MIMO-OFDM Systems" and "Real-Time FPGA Implementation of Massive MIMO Detection for 5G NR Platforms".
• Other authors have some prior works on OFDM transceiver implementation and optimization using FPGAs.

In summary, the authors are faculty and researchers in the ECE department at Drexel University with significant expertise in wireless communications, signal processing, and FPGA-based implementations. Dandekar in particular has an extensive background that is directly relevant to this OTFS work.